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Hsb Ip Create Top

NVIDIAOfficialCreated by Holoscan TeamDistributed by NVIDIA

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  • Workflow
  • Software development
  • Apache-2.0
  • Medium risk
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From the author

Create or explain fixed-format HSB FPGA_top.sv wrappers from validated HOLOLINK_def.svh files. Do not use for def generation or validation.
— the description by Holoscan Team

AutoGineer summary

Written by AutoGineer from the skill’s own files, not by the author

This skill provides a structured workflow to generate an FPGA_top.sv scaffold, which serves as the top-level wrapper for HSB IP. It ensures that the generated code adheres to a fixed format, including necessary license headers, module shells, and signal declarations derived from a validated HOLOLINK_def.svh file. The skill is designed to work either as a standalone tool or as a follow-up to the hsb-ip-def skill, ensuring that integration scaffolds are consistent with the underlying IP configuration.

What it does

  • Generates a fixed-format FPGA_top.sv scaffold.
  • Instantiates the HOLOLINK_top module.
  • Declares HSB-facing signals based on validated HOLOLINK_def.svh macros.
  • Provides TODO comments for top-level integration points.
  • Supports both live HSB IP source extraction and bundled known-revision references.

When to use it

  • When you have a validated HOLOLINK_def.svh and need to create a top-level wrapper.
  • When you need to ensure your FPGA top-level structure follows established HSB integration standards.
  • When transitioning from IP definition to top-level system integration.

Advantages

  • Ensures consistent top-level structure across different HSB IP configurations.
  • Automates the tedious process of declaring complex HSB-facing signal groups.
  • Maintains strict adherence to port shapes and interface requirements.
  • Reduces integration errors by using validated defs as the source of truth.

Usage examples

“Create an FPGA_top.sv scaffold using my validated HOLOLINK_def.svh.”
The agent will verify the defs file, determine the appropriate port map source, and generate the fixed-format SystemVerilog scaffold.
“I just finished generating my defs with hsb-ip-def, can you create the top-level wrapper now?”
The agent will consume the existing context from the def-skill handoff and proceed directly to generating the FPGA_top.sv scaffold.

Install

  1. Download the skill as a ZIP:

    https://mp-staging.autogineer.com/agent-skills/nvidia/hsb-ip-create-top/download

  2. Unzip it into the cross-client skills folder of your project:

    mkdir -p .agents/skills && unzip hsb-ip-create-top.zip -d .agents/skills

Documentation by Holoscan Team

HSB IP Create Top Skill

Purpose

Create a fixed-format SystemVerilog top-level scaffold that instantiates HOLOLINK_top and declares the HSB-facing signals required by a validated HOLOLINK_def.svh.

This skill owns only the top-level scaffold around the HSB IP:

  • SPDX/Apache license header

  • HOLOLINK_def.svh include

  • FPGA_top module shell

  • HSB-facing signal declarations

  • HOLOLINK_top instantiation

  • comments/TODOs for top-level integration

Use hsb-ip-def for HOLOLINK_def.svh generation and validation. Do not create or validate the defs file here.

Prerequisites

  • A validated HOLOLINK_def.svh path or pasted file content is required before generating FPGA_top.sv.

  • Live HOLOLINK_top.sv source is preferred when source-sensitive port extraction is needed; bundled references cover known rev 16'h2604 and compatible rev 16'h2603.

  • The user must provide or accept the output path when writing a scaffold file.

Instructions

  • Require a validated HOLOLINK_def.svh before creating FPGA_top.sv. If the user does not have one, invoke or direct them to hsb-ip-def first.

  • Treat live HOLOLINK_top.sv as the source of truth for ports, directions, macro gates, and IP revision whenever it is available.

  • First classify the request as Standalone Create Top, Def-Skill Handoff, or Explain. Load only the references required for that workflow and do not re-read the same reference just to reconfirm formatting.

  • Use references/fixed-format.md as the baked formatting and naming style. Do not inspect example top-level files just to confirm formatting during normal generation.

  • Emit a fixed-format scaffold, not a complete project top. Because the surrounding design is unknown, the generated FPGA_top module normally has no top-level ports.

  • Derive active signal groups from the validated defs file. Do not connect ports that are absent from HOLOLINK_top under the active macro set.

  • Preserve HOLOLINK_top port shapes exactly: keep packed vector widths before the signal name and unpacked interface-array dimensions after the signal name.

  • When using bundled known-rev references, still preserve the signal shapes in references/fixed-format.md, including unpacked arrays for multi-interface *_tdata, *_tkeep, and *_tuser buses and the APB shape documented there.

  • Use sensor-agnostic language. Say "sensor data", "sensor interface", and "stream"; use camera-specific language only after the user says the design is camera-specific.

  • Ask one plain-language question per turn when information is missing. Keep source-selection questions as plain-language prompts rather than radio buttons, structured choices, or multi-question prompts.

  • Do not invent project-specific integration details. Leave concise TODO comments where the surrounding design must connect to HSB.

  • For packetizer comments in FPGA_top.sv, use generic wording such as "data manipulation behavior".

  • In final summaries, include the defs validation/source status, the port-map source used, and the emitted HSB signal groups. Do not enumerate what is outside the scaffold's scope. Use only this generic note: "This file is a reference/template for hooking up top-level signals and companion IP to the HSB IP."

Live HSB IP Source Policy

Prefer live HSB IP source over bundled references whenever the user's workspace provides it. The bundled references describe known rev 16'h2604 and backward-compatible rev 16'h2603; live source is the authority for the checked-out IP.

When source is available:

  1. Locate <hsb-ip-root>/top/HOLOLINK_top.sv. Known roots include hw/nvcpu_dgx_fpga/vrtl/hololink/ and public-release fpga/nv_hsb_ip/.

  2. Read HOLOLINK_REV and HOLOLINK_BACKWARD_COMPAT_REV from HOLOLINK_top.sv.

  3. Read the HOLOLINK_top module declaration to confirm port names, directions, widths, ordering, and ifdef/ifndef gates.

  4. If the rev is newer, unknown, or the live source disagrees with this skill's references, state the mismatch. Trust the live source for IO extraction and warn that bundled references may need an update.

When no source is available, use the bundled references as known-revision guidance and say the scaffold is based on the skill's supported HSB IP rev. If the user already authorized using the bundled known-rev port reference when no checkout is obvious, do a brief search of obvious roots and then proceed with bundled references instead of asking the live-source question.

If the source root is not obvious, ask conversationally in one turn:

Do you have a current HSB IP `HOLOLINK_top.sv` source checkout you want me to use for port extraction, or should I use the skill's bundled known-rev port reference?

Accept either a path or a "use bundled reference" answer.

Reference Loading

Load only the reference needed for the user's task:

FileWhen to load
references/source-policy.mdFinding live HSB IP source, handling unknown revisions, or deciding source/reference precedence
references/fixed-format.mdGenerating or explaining the fixed FPGA_top.sv scaffold format
references/handoff-contract.mdStandalone prerequisite handling or def-skill handoff behavior

Workflow Decision

  1. If invoked by hsb-ip-def after a successful defs generation/validation, use Def-Skill Handoff.

  2. If the user directly asks to create FPGA_top.sv, instantiate HOLOLINK_top, or make a top-level wrapper, use Standalone Create Top.

  3. If the user asks about version handling, port groups, or why a signal appears, use Explain.

Standalone Create Top

Use this when the user invokes this skill directly.

Steps:

  1. Ask for the path to a validated HOLOLINK_def.svh, or accept pasted content. If the user does not have a defs file, stop and direct them to hsb-ip-def to create and validate it first.

  2. If validation status is unknown, invoke or direct the user to hsb-ip-def validation. Do not proceed from an unvalidated defs file.

  3. If the HSB IP source root is not obvious and source-sensitive output is needed, ask the live-source question from "Live HSB IP Source Policy" unless the user already authorized bundled known-rev fallback. Do not show path options as radio buttons. The known roots are search hints for the agent, not choices to force on the user.

  4. Load references/source-policy.md and references/fixed-format.md.

  5. Derive the active macro set from the validated defs file.

  6. Derive or verify HOLOLINK_top port groups from live source when available.

  7. Produce FPGA_top.sv in the fixed format. If writing a file, default filename is FPGA_top.sv unless the user provides a path.

  8. Explain that the result is an HSB integration scaffold. Use the generic reference/template note in ## Instructions; do not enumerate what is outside the scaffold's scope.

Def-Skill Handoff

Use this when hsb-ip-def has just completed a validated HOLOLINK_def.svh and the user chooses to create a matching top-level scaffold.

Steps:

  1. Accept the validated defs file path/content and any known profile/source-root context from hsb-ip-def.

  2. Do not re-ask for defs-file decisions already completed by the def skill.

  3. Ask only for missing top-generation facts, such as output path or HSB IP source root when needed. If source root is missing, ask the live-source question from "Live HSB IP Source Policy" unless the user already authorized bundled known-rev fallback; do not use radio buttons or structured choices.

  4. Load references/handoff-contract.md and references/fixed-format.md.

  5. Generate the fixed-format FPGA_top.sv scaffold from the active defs macros and live HOLOLINK_top.sv when available.

  6. Return a concise summary of which HSB signal groups were emitted, then use the generic reference/template note in ## Instructions. Do not enumerate what is outside the scaffold's scope.

Explain

Use this when the user asks why a port or signal group appears, how macro settings affect the top scaffold, or how the skill handles IP revisions.

Steps:

  1. For port questions, prefer live HOLOLINK_top.sv when available. Otherwise load references/fixed-format.md.

  2. For revision/source questions, load references/source-policy.md.

  3. For defs-file macro meaning, defer to hsb-ip-def.

Troubleshooting

  • Missing or unvalidated defs file: stop before generation and send the user to hsb-ip-def validation.

  • Unknown or newer HSB IP revision: prefer live source if available, state the mismatch, and warn that bundled references may need updates.

  • Port missing under the active macro set: omit that connection and explain which validated def macro disabled the signal group.

Examples

  • Use hsb-ip-create-top to create an FPGA_top.sv scaffold from my validated HOLOLINK_def.svh. Use the bundled known-rev port reference if no HSB IP source checkout is obvious. Treat as Standalone Create Top, require the validated defs file, load references/source-policy.md and references/fixed-format.md, use bundled known-rev ports after a brief source search, and report the defs status, port-map source, and emitted signal groups.

  • Create a top-level FPGA_top.sv wrapper for HSB, but I do not have a HOLOLINK_def.svh yet. Stop before generation, direct the user to hsb-ip-def, and ask for a validated defs file path or content before proceeding.

  • Why does the generated FPGA_top.sv include different HSB signal groups depending on my HOLOLINK_def.svh macros? Treat as Explain, say that validated defs macros gate the HSB-facing signal groups and that the live HOLOLINK_top.sv port map wins when available; defer detailed macro semantics to hsb-ip-def.

Limitations

  • Do not generate HOLOLINK_def.svh.

  • Do not validate full HOLOLINK_def.svh files.

  • Do not generate project-specific integration outside the HSB-facing scaffold.

  • Do not infer signal meanings, polarity, sources, or behavior outside the HSB port map.

  • Do not copy example project logic into the scaffold unless the user explicitly requests project-specific adaptation.

Files

references/fixed-format.md

Fixed FPGA_top.sv Format

Use this reference when generating the top-level scaffold.

Output Intent

The generated file is an HSB integration scaffold, not a complete project top. It instantiates HOLOLINK_top and declares HSB-facing signals according to the active HOLOLINK_def.svh macros. This file is a reference/template for hooking up top-level signals and companion IP to the HSB IP.

Required Order

Emit sections in this order:

  1. SPDX/Apache license header.

  2. `include "HOLOLINK_def.svh".

  3. module FPGA_top declaration, normally with no top-level ports.

  4. HSB-facing declarations in fixed section order.

  5. HOLOLINK_top instantiation.

  6. endmodule.

Module Shell

Use this shape unless the user explicitly asks for board ports:

`include "HOLOLINK_def.svh"

module FPGA_top
  import HOLOLINK_pkg::*;
  import apb_pkg::*;
#(
  // Build identifier reported by HSB status/version registers:
  // BUILD_REV[47:16] = build date, BUILD_REV[15:0] = build revision.
  parameter BUILD_REV = 48'h0
)();

Comment Banner

Use this baked banner style:

//------------------------------------------------------------------------------
// Section Name
//------------------------------------------------------------------------------

Inside the HOLOLINK_top port map, use the same banner style for major groups and concise single-line comments for subgroups.

Signal Shape Rules

Preserve the HOLOLINK_top.sv declaration shape. Keep packed vector widths before the signal name and keep unpacked interface-array dimensions after the signal name. Do not collapse these ports into packed two-dimensional vectors.

Use this shape for multi-interface data buses:

logic [`DATAPATH_WIDTH-1:0]   sif_rx_axis_tdata [`SENSOR_RX_IF_INST-1:0];
logic [`DATAKEEP_WIDTH-1:0]   sif_rx_axis_tkeep [`SENSOR_RX_IF_INST-1:0];
logic [`DATAUSER_WIDTH-1:0]   sif_rx_axis_tuser [`SENSOR_RX_IF_INST-1:0];

logic [`DATAPATH_WIDTH-1:0]   sif_tx_axis_tdata [`SENSOR_TX_IF_INST-1:0];
logic [`DATAKEEP_WIDTH-1:0]   sif_tx_axis_tkeep [`SENSOR_TX_IF_INST-1:0];
logic [`DATAUSER_WIDTH-1:0]   sif_tx_axis_tuser [`SENSOR_TX_IF_INST-1:0];

logic [`HOST_WIDTH-1:0]       hif_rx_axis_tdata [`HOST_IF_INST-1:0];
logic [`HOSTKEEP_WIDTH-1:0]   hif_rx_axis_tkeep [`HOST_IF_INST-1:0];
logic [`HOSTUSER_WIDTH-1:0]   hif_rx_axis_tuser [`HOST_IF_INST-1:0];
logic [`HOST_WIDTH-1:0]       hif_tx_axis_tdata [`HOST_IF_INST-1:0];
logic [`HOSTKEEP_WIDTH-1:0]   hif_tx_axis_tkeep [`HOST_IF_INST-1:0];
logic [`HOSTUSER_WIDTH-1:0]   hif_tx_axis_tuser [`HOST_IF_INST-1:0];

Do not emit this packed 2-D form for those buses:

logic [`SENSOR_RX_IF_INST-1:0][`DATAPATH_WIDTH-1:0] sif_rx_axis_tdata;
logic [`HOST_IF_INST-1:0][`HOST_WIDTH-1:0] hif_rx_axis_tdata;

Use packed vectors for one-bit-per-interface signals:

logic [`SENSOR_RX_IF_INST-1:0] sif_rx_clk;
logic [`SENSOR_RX_IF_INST-1:0] sif_rx_rst;
logic [`SENSOR_RX_IF_INST-1:0] sif_rx_axis_tvalid;
logic [`SENSOR_RX_IF_INST-1:0] sif_rx_axis_tlast;
logic [`SENSOR_RX_IF_INST-1:0] sif_rx_axis_tready;

logic [`HOST_IF_INST-1:0] hif_rx_axis_tvalid;
logic [`HOST_IF_INST-1:0] hif_rx_axis_tlast;
logic [`HOST_IF_INST-1:0] hif_rx_axis_tready;

Use the APB register interface shape from HOLOLINK_top.sv; only psel, pready, and pserr are per-REG_INST vectors, and only prdata is a 32-bit unpacked array:

logic [`REG_INST-1:0] apb_psel;
logic                 apb_penable;
logic [31:0]          apb_paddr;
logic [31:0]          apb_pwdata;
logic                 apb_pwrite;
logic [`REG_INST-1:0] apb_pready;
logic [31:0]          apb_prdata [`REG_INST-1:0];
logic [`REG_INST-1:0] apb_pserr;

When ENUM_EEPROM is undefined, declare the host-indexed MAC array as:

logic [47:0] mac_addr [`HOST_IF_INST-1:0];

Declaration Sections

Emit these sections in order, omitting groups that are absent under the active defs macro set:

  1. Clock and Reset

    • sys_rst

    • apb_clk, apb_rst

    • hif_clk, hif_rst

    • ptp_clk, ptp_rst

    • sif_rx_clk, sif_rx_rst only when SENSOR_RX_IF_INST is defined

    • sif_tx_clk, sif_tx_rst only when SENSOR_TX_IF_INST is defined

    Comment sif_rx_rst and sif_tx_rst at the declaration site. They are HSB outputs generated by HOLOLINK_top / reset_gen in the corresponding sensor interface clock domain.

  2. User APB Interface

    • apb_psel

    • apb_penable

    • apb_paddr

    • apb_pwdata

    • apb_pwrite

    • apb_pready

    • apb_prdata

    • apb_pserr

  3. Board Enumeration

    • Only when ENUM_EEPROM is undefined:

      • mac_addr [HOST_IF_INST-1:0]

      • board_sn

      • enum_vld

  4. Initialization

    • init_done

  5. Sensor RX Interface

    • Only when SENSOR_RX_IF_INST is defined:

      • sif_rx_axis_tvalid

      • sif_rx_axis_tlast

      • sif_rx_axis_tdata

      • sif_rx_axis_tkeep

      • sif_rx_axis_tuser

      • sif_rx_axis_tready

  6. Sensor TX Interface

    • Only when SENSOR_TX_IF_INST is defined:

      • sif_tx_axis_tvalid

      • sif_tx_axis_tlast

      • sif_tx_axis_tdata

      • sif_tx_axis_tkeep

      • sif_tx_axis_tuser

      • sif_tx_axis_tready

  7. Sensor Event

    • sif_event

  8. Host Interface

    • hif_rx_axis_* for data entering HSB from the host side

    • hif_tx_axis_* for data leaving HSB toward the host side

  9. Peripheral Interfaces

    • SPI only when SPI_INST is defined

    • I2C only when I2C_INST is defined

    • UART only when UART_INST is defined

  10. GPIO

    • gpio_in

    • gpio_out

    • gpio_dir

  11. Sensor Reset

    • sw_sys_rst

    • sw_sen_rst

  12. PTP

    • Always declare ptp_clk and ptp_rst in Clock and Reset.

    • When EXT_PTP is undefined, declare ptp_sec, ptp_nanosec, and pps as outputs from HSB.

    • When EXT_PTP is defined, declare board-provided ptp_sec and ptp_nanosec signals and connect them to the live-source i_ptp_sec and i_ptp_nanosec ports.

Instantiation Rules

  • Instantiate HOLOLINK_top as u_hololink_top.

  • Pass .BUILD_REV ( BUILD_REV ).

  • Preserve the HOLOLINK_top port order from live source when available.

  • Include only ports present under the active macro set.

  • Avoid trailing comma on the final active port connection.

  • Use the same section order as the declarations.

  • Do not connect absent optional ports.

Placeholder Policy

Do not invent project-specific drivers. Prefer declarations plus TODO comments:

// TODO: Drive sys_rst from board reset and clock/reset logic.
logic sys_rst;

Use tie-offs only for clearly inert placeholders when the scaffold would otherwise be misleading, and call them out as placeholders. Do not tie off active sensor, host, APB, or clock paths as if that were complete integration.

Packetizer Comment Language

When packetizer fields are enabled, summarize them in terms of data manipulation behavior:

// TODO: Connect sif_rx_axis_* to the sensor-side source. Packetizer enabled
// (SIF_RX_PACKETIZER_EN[0]=1) with VP_COUNT=4, VP_SIZE=128,
// SORT_RESOLUTION=16, NUM_CYCLES=1 -- runtime APB programming routes
// virtual ports and controls the data manipulation behavior.

Generated comments should keep packetizer wording generic and describe the configured data manipulation behavior.

Requirements and compatibility

Works with: Claude Code, Claude apps, OpenAI Codex, GitHub Copilot, Cursor, Gemini CLI, Kiro, OpenCode, Goose, Amp, Roo Code, JetBrains Junie, Factory Droid, Devin (ex-Windsurf), Mistral Vibe, OpenHands, Letta

“Works with” means the tool reads the open Agent Skills format; a skill written for one tool may use features others lack.

The author says: Targets HSB IP rev 16'h2604; backward-compatible with 16'h2603. Prefer live HSB IP source when available; warn on unknown revisions. Designed to work standalone or as a companion to hsb-ip-def.

Security

What our scanner noticed· Medium risk

  • Large base64-encoded blobs

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Attribution and licence

Created by
Holoscan Team
Publisher
NVIDIA (Official)
Distributed by
NVIDIA
Source
NVIDIA/skills · skills/hsb-ip-create-top · commit fce3cca
Licence
Apache License 2.0 (redistribution allowed)
  • LICENSE (added by AutoGineer from LICENSE-APACHE)
  • ATTRIBUTION.md (written by AutoGineer)
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