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Jetson Customize Mgbe

NVIDIAOfficialCreated by Jetson TeamDistributed by NVIDIA

  • Skill
  • Tool integration
  • Cloud and DevOps
  • Apache-2.0
  • Medium risk
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From the author

Enable Jetson Thor 25G/10G/1G MGBE QSFP via kernel-DT overlay. Do NOT use for UPHY lane allocation or ODMDATA edits.
— the description by Jetson Team

AutoGineer summary

Written by AutoGineer from the skill’s own files, not by the author

This skill provides a structured workflow for enabling MGBE (Multi-Gigabit Ethernet) controllers on Jetson Thor platforms. It handles the creation of kernel-DT overlays to configure MGBE interfaces for 25G, 10G, or 1G fiber paths, including PHY plumbing. It is designed to work in conjunction with UPHY lane allocation and pinmux customization skills, ensuring that the hardware configuration is correctly represented in the device tree without interfering with ODMDATA or UPHY lane settings.

What it does

  • Generates kernel-DT overlay fragments to enable MGBE controllers.
  • Configures PHY modes and MDIO/I2C settings for external PHYs.
  • Validates HSIO pin configurations for MGBE signals.
  • Ensures correct device tree compatibility matching for UEFI plugin-manager.
  • Provides a structured audit trail for hardware configuration changes.
  • Integrates with existing BSP source repositories and overlay trackers.

When to use it

  • When enabling 25G, 10G, or 1G Ethernet on a custom carrier board.
  • When an MGBE controller is configured but reports state DOWN or NO-CARRIER.
  • After successfully running jetson-customize-uphy for lane allocation.
  • When integrating an external MDIO PHY with a QSFP cage.

Advantages

  • Prevents common configuration errors by enforcing prerequisite checks.
  • Maintains clean separation between UPHY, pinmux, and MGBE configurations.
  • Automates the complex process of device tree overlay generation.
  • Ensures compatibility with the Jetson BSP build system.

Usage examples

“Enable 25G QSFP on mgbe0 for my custom Thor carrier.”
The agent initiates the MGBE configuration workflow, validates the UPHY allocation, and generates the necessary kernel-DT overlay for the 25G interface.
“My 10G fiber link is not coming up on mgbe1.”
The agent checks the current device tree status, verifies the PHY mode and MDIO settings, and helps identify if the issue is in the overlay or pinmux.

Install

  1. Download the skill as a ZIP:

    https://mp-staging.autogineer.com/agent-skills/nvidia/jetson-customize-mgbe/download

  2. Unzip it into the cross-client skills folder of your project:

    mkdir -p .agents/skills && unzip jetson-customize-mgbe.zip -d .agents/skills

Documentation by Jetson Team

Customize MGBE / 25G QSFP

Overview

Thor T264 exposes mgbe0..mgbe3. On a custom carrier, the 25G QSFP cage (or 10G / 1G fiber path) is wired to one of them through SerDes — with or without an external MDIO PHY in front of the cage. This skill renders the kernel-DT overlay that pairs the BPMP allocation with kernel-side status="okay" + PHY plumbing on &mgbeN.

Out of scope:

  • UPHY lane allocation — owned by /jetson-customize-uphy. Refuse if the chosen uphy1-config-N doesn't allocate the target MGBE.

  • All ODMDATA tokens (mgbeN-speed-*, sub-node mgbeN_status=*) — owned by /jetson-customize-uphy in its single atomic ODMDATA commit. This skill MUST NOT touch ODMDATA=.

Output is one commit to the composite custom overlay .dts in the bsp_sources/ hardware repo. /jetson-build-source compiles the composite to .dtbo and owns its Makefile + flash-conf registration.

When to invoke

  • The user says "enable 25G", "configure QSFP", "set MGBE PHY mode", "wire MGBE to QSFP", or asks to bring up a 10G / 1G fiber path.

  • Cold boot succeeds but ip link show mgbe<N> reports state DOWN or NO-CARRIER on the configured controller, OR the controller never appears at all.

  • jetson-customize-uphy ran with uphy1-config-8 (or another config allocating MGBE) and you now need to bring up the per-controller side.

Prerequisites:

  • Active profile selected with reference_devkit: (Thor) + custom_carrier: blocks.

  • <source.root_path>/Linux_for_Tegra/.git exists (/jetson-init-source).

  • /jetson-derive-carrier has run — carrier flash-conf fork is in the overlay tracker.

  • /jetson-customize-uphy chose a UPHY config that allocates the target MGBE controller's lanes (uphy1-config-8 on Thor for MGBE0..3 25G).

  • Source-of-truth docs registered or supplied at prompt: Adaptation Guide, Module Design Guide, SoC TRM.

  • When custom_carrier: is present, both documents.custom_carrier_schematic AND documents.custom_carrier_pinmux_xls are REQUIRED. Refuse the run if either is missing — MGBE routing on a custom carrier cannot be guessed. Reference-devkit-only profiles skip this check.

  • dtc on PATH.

Procedure

See references/procedure.md for the full step-by-step procedure (Steps 1–8). Summary:

  1. Resolve active target + documents. Validate active profile, custom_carrier, overlay tracker; locate the relevant Adaptation Guide chapter and pinmap.

  2. Per-controller question loop. AskUserQuestion driven by questions.json (controller, phy_mode, attach kind, I²C bus/addr, reset GPIO, compatible_list).

  3. Derive max-speed from phy_mode. Decompile the BPMP DTB to pick sub-node vs top-level token grammar; cite the inspection in notes.

  4. Verify HSIO pins + auto-fix. Run pin_verifier.py for MDC/MDIO/RESET/INT; surface mismatches and route to /jetson-customize-pinmux.

  5. (no ODMDATA edits.) MGBE ODMDATA tokens are emitted by /jetson-customize-uphy. Step 5 only records the BPMP DTB token-form inspection (sub-node vs top-level) in notes[] for audit.

  6. Append composite-overlay fragments. Write one fragment per controller into the composite custom overlay .dts; obey the /* custom-bsp: mgbe:mgbe... */ marker contract; run the cpp/dtc/fdtoverlay pre-flight.

  7. (Reserved.) Sibling-skill ordering / cross-cutting validation.

  8. Run-state sidecar + summary + next-step chain. Write <profile-stem>.jetson-customize-mgbe.json and emit the one-line + table summary, then drive the downstream chain via sequential AskUserQuestion prompts per references/procedure.md Step 8. Never substitute a printed "Next step: …" line for the prompts.

Gotchas

  • Stock Thor BPMP DTB has no /mgbe/mgbe@N subtree — only mgbe<N>-speed under /uphy. The mgbe<N>_status=disabled sub-node token is silently rejected on these releases; the whole ODMDATA line is then dropped at flash time. Always decompile BPMP DTB (Step 3) before emitting; use the top-level dashed form (mgbe<N>-speed-del to remove, mgbe<N>-speed-25G to set) when the sub-node isn't there. Same wrong-form failure surface as jetson-customize-uphy.

  • mdio child needs both #address-cells = <1> AND #size-cells = <0> when phy_attach_kind=="phy". Missing either → kernel rejects phy@<addr> reg property at probe; MGBE never comes up.

  • Overlay root compatible must intersect live DT compatible. UEFI plugin-manager filters by compatible match. A mismatched overlay is silently skipped — flash succeeds, MGBE stays disabled, no error in dmesg. Always sanity-check against /proc/device-tree/compatible on a booted reference DUT.

  • OVERLAY_DTB_FILE ordering is jetson-build-source's problem, not this skill's. This skill never touches the carrier flash conf. The composite custom overlay is registered (by /jetson-build-source Step 5.0a) AFTER the platform *-dynamic.dtbo, which is the correct ordering. If you find yourself appending OVERLAY_DTB_FILE+= in this skill, you're duplicating ownership — stop, and let the build skill do it.

  • UPHY lane allocation is jetson-customize-uphy's job. If the chosen uphy1-config-N doesn't allocate lanes for the target MGBE controller, BL31 SError (fmon_update_config: detected fault 0x80) on cold boot. Always run /jetson-customize-uphy first; cite the chosen uphy1-config-N in this skill's run-summary notes[].

  • Don't disable a stock-okay controller via ODMDATA alone. Same rule as jetson-customize-uphy: mgbe<N>_status=disabled for a controller that's already disabled in BPMP DTB is a no-op the parser may treat as ambiguous → drops the rest of the ODMDATA line. Disable via the kernel-DT overlay (status="disabled") only.

  • Don't touch the upstream BSP at <bsp_image.root_path>. All edits land in the overlay tracker / bsp_sources mono-repo under the pristine + customization commit pattern.

  • JSON sidecar is structured state, not authoritative. Same caveat as jetson-customize-uphy: ODMDATA + overlay .dts + two git commits are the device-facing outputs; the sidecar is for tooling and idempotency only.

References

  • questions.json — Q-1..Q-8 prompt schema consumed by Step 2.

  • ../../scripts/pin_verifier.py — shared HSIO pin verifier (Step 4).

  • ../../references/platform_template.yaml — documents: block consumed by Step 1.

  • ../../context/bsp-customization-workflow.md — overlay edit protocol (batched pristine + customization commit).

  • ../jetson-customize-uphy/SKILL.md — sibling skill that owns UPHY lane allocation. Must run before this skill to set uphy1-config-N for MGBE-allocated configurations.

  • ../jetson-customize-pinmux/SKILL.md — sibling skill invoked by Step 4 (with operator confirmation) to fix pin SFIO mismatches.

  • ../jetson-derive-carrier/SKILL.md — must run first; produces the carrier flash-conf fork edited in Step 5 and the carrier base overlay this skill orders after.

  • ../jetson-init-source/SKILL.md — produces the overlay tracker + bsp_sources repo this skill commits into.

Files

references/questions.json

{
  "schema_version": 1,
  "io": "mgbe",
  "questions": [
    {
      "id": "controller_selection",
      "header": "MGBE controllers",
      "question": "Which MGBE controller(s) on the module are wired to the QSFP cage / 25G path? (multi-select)",
      "multiSelect": true,
      "options": [
        {"label": "mgbe0", "description": "Thor MGBE0 (most common QSFP path on reference carriers)"},
        {"label": "mgbe1", "description": "Thor MGBE1"},
        {"label": "mgbe2", "description": "Thor MGBE2"},
        {"label": "mgbe3", "description": "Thor MGBE3"}
      ],
      "guidance": "Check the carrier schematic — the QSFP cage's SerDes pair lands on exactly one MGBE controller. UPHY lane allocation for that controller is set at the platform/SKU level via the `uphy0-config-N` ODMDATA token (handled by /modify-uphy, not here). If the schematic ingest under <KB>/schematic/<carrier>_nets.json names the controller (e.g. `MGBE0_TX_*`/`MGBE0_RX_*` nets near the QSFP refdes), prefer that signal evidence."
    },
    {
      "id": "phy_mode",
      "header": "PHY mode",
      "question": "Per controller, which PHY mode should the kernel negotiate?",
      "per_controller": true,
      "options": [
        {"label": "25g-r", "description": "25 Gb/s SerDes (Recommended for QSFP 25G)"},
        {"label": "10g-kr", "description": "10 Gb/s KR backplane"},
        {"label": "1000base-x", "description": "1 Gb/s SerDes (legacy fiber path)"}
      ]
    },
    {
      "id": "phy_attach_kind",
      "header": "PHY attach",
      "question": "Per controller, is there an external board PHY in front of the cage, or is the SerDes wired directly to the QSFP cage?",
      "per_controller": true,
      "options": [
        {"label": "phy", "description": "Board PHY between MGBE SerDes and the QSFP cage. Skill emits phy-handle, an `mdio { phy@<addr> { reg=<addr>; }; }` child node, and nvidia,phy-reset-gpios."},
        {"label": "direct", "description": "MGBE SerDes wired straight to the QSFP cage (no MDIO PHY between). Skill omits phy-handle / mdio / phy-reset-gpios; phy-mode + nvidia,max-speed remain."}
      ]
    },
    {
      "id": "phy_i2c_bus",
      "header": "PHY I²C bus",
      "question": "Which I²C controller node is the PHY hung off? (only when phy_attach_kind == 'phy')",
      "per_controller": true,
      "ask_only_if": "phy_attach_kind == 'phy'",
      "options": [
        {"label": "i2c@3160000", "description": "Thor i2c0"},
        {"label": "i2c@c240000",  "description": "Thor i2c1"},
        {"label": "i2c@3180000",  "description": "Thor i2c2"},
        {"label": "i2c@3190000",  "description": "Thor i2c3"},
        {"label": "i2c@31a0000",  "description": "Thor i2c4"},
        {"label": "i2c@31b0000",  "description": "Thor i2c5"},
        {"label": "i2c@31c0000",  "description": "Thor i2c6"},
        {"label": "i2c@c250000",  "description": "Thor i2c7"}
      ],
      "guidance": "Pick the I²C controller whose SDA/SCL nets reach the PHY refdes per the schematic. The node name is the unit-address of the I²C controller in the kernel DT — it appears under /bus@0/i2c@... at runtime."
    },
    {
      "id": "phy_i2c_addr_hex",
      "header": "PHY I²C address",
      "question": "7-bit I²C address of the PHY in hex (e.g. 0x56). (only when phy_attach_kind == 'phy')",
      "per_controller": true,
      "ask_only_if": "phy_attach_kind == 'phy'",
      "validation": "^0x[0-7][0-9a-fA-F]$",
      "guidance": "Read the PHY datasheet section on strap pins — the address is set by ADDR0..ADDR2 strap resistors at power-on. Cross-check against `i2cdetect -y -r <bus>` on a working reference board."
    },
    {
      "id": "phy_reset_gpio_offset",
      "header": "PHY reset GPIO offset",
      "question": "Per controller, GPIO offset (decimal) of the PHY reset line within the chosen bank.",
      "per_controller": true,
      "validation": "^[0-9]+$",
      "guidance": "The offset is the integer that appears in the DT phandle expression `<&gpio_main OFFSET 0>` (or `&gpio_aon`). Look up the Thor pinmap (<KB>/pinmap/<carrier>.json or the Thor SoC pinmux spreadsheet) for the exact gpio offset matching the carrier net name."
    },
    {
      "id": "phy_reset_gpio_bank",
      "header": "PHY reset GPIO bank",
      "question": "Per controller, which GPIO bank holds the PHY reset line?",
      "per_controller": true,
      "options": [
        {"label": "gpio_main", "description": "Main GPIO controller (most carrier GPIOs)"},
        {"label": "gpio_aon",  "description": "Always-on GPIO controller (AON domain pins)"}
      ]
    },
    {
      "id": "compatible_list",
      "header": "Match boards",
      "question": "Which root `compatible` strings should this overlay match? (Pick at least one that matches the live DUT's /proc/device-tree/compatible — UEFI plugin-manager will skip the overlay otherwise.)",
      "multiSelect": true,
      "key": "platform_compatible_list",
      "options_source": "session.platform_compatible_list || this.platform_defaults[session.platform]",
      "platform_defaults": {
        "thor": [
          "nvidia,p3971-0089+p3834-0008",
          "nvidia,p3971-0050+p3834-0005",
          "nvidia,p3971-0080+p3834-0008",
          "nvidia,p3971-0080+p3834-0000"
        ]
      },
      "required": true,
      "must_match_live_compatible": true,
      "guidance": "Mirrors modify-camera Q-CON-3 / modify-pcie compatible_list. Verify with `cat /proc/device-tree/compatible | tr '\\0' '\\n'` on the booted DUT before answering. When session.platform_compatible_list is already populated (from a prior /custom-bsp clone or /modify-camera run), reuse those values rather than re-asking.",
      "ask_only_if": "session.platform_compatible_list is empty AND no platform_defaults match"
    }
  ]
}

Requirements and compatibility

Written for: Claude Code

Works with: Claude Code, Claude apps, OpenAI Codex, GitHub Copilot, Cursor, Gemini CLI, Kiro, OpenCode, Goose, Amp, Roo Code, JetBrains Junie, Factory Droid, Devin (ex-Windsurf), Mistral Vibe, OpenHands, Letta

“Works with” means the tool reads the open Agent Skills format; a skill written for one tool may use features others lack.

Needs: Names Claude Code tools, Needs Node.js

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Attribution and licence

Created by
Jetson Team
Publisher
NVIDIA (Official)
Distributed by
NVIDIA
Source
NVIDIA/skills · skills/jetson-customize-mgbe · commit fce3cca
Licence
Apache License 2.0 (redistribution allowed)
  • LICENSE (added by AutoGineer from LICENSE-APACHE)
  • ATTRIBUTION.md (written by AutoGineer)
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