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Jetson Customize Pcie

NVIDIAOfficialCreated by Jetson TeamDistributed by NVIDIA

  • Skill
  • Workflow
  • Software development
  • Apache-2.0
  • Medium risk
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From the author

Per-controller PCIe enable / disable / lanes / link-speed for a Jetson Thor or Orin custom carrier via ODMDATA + kernel-DT overlay. Do NOT use for UPHY lane allocation or endpoint-mode bring-up.
— the description by Jetson Team

AutoGineer summary

Written by AutoGineer from the skill’s own files, not by the author

This skill manages the per-controller configuration for PCIe on Jetson Thor and Orin platforms. It operates by generating kernel-DT overlay fragments to define controller status, lane width, and link speed. It ensures consistency between the kernel device tree and the BPMP-side ODMDATA settings, which are managed by the sibling jetson-customize-uphy skill. The process involves topology analysis, pin verification against carrier schematics, and the generation of overlay commits for the BSP source repository.

What it does

  • Analyzes PCIe topology differences between reference devkits and custom carriers.
  • Verifies required PCIe sideband signals (CLKREQ, RST) against carrier pinmaps and schematics.
  • Generates kernel-DT overlay fragments to enable or configure PCIe controllers.
  • Performs consistency checks between kernel-DT overlays and ODMDATA settings.
  • Maintains a run-state JSON sidecar to track configuration history.
  • Integrates with the broader BSP customization workflow for Jetson platforms.

When to use it

  • When configuring PCIe controllers on a custom Jetson carrier board.
  • When a PCIe slot or M.2 receptacle fails to enumerate after flashing.
  • When PCIe links train at incorrect widths or speeds.
  • After running jetson-customize-uphy to reallocate lanes across controllers.

Advantages

  • Ensures hardware-software alignment through schematic and pinmap verification.
  • Prevents configuration drift by cross-checking ODMDATA and kernel-DT settings.
  • Automates the creation of complex kernel-DT overlay fragments.
  • Provides a structured, repeatable workflow for custom carrier bring-up.

Usage examples

“Configure PCIe controller C3 for my custom Orin carrier.”
The agent will analyze the current UPHY state, verify the carrier pinmap for C3, and generate the necessary kernel-DT overlay fragment to enable the controller.
“My M.2 slot is training at x1 speed instead of x4, please fix it.”
The agent will compare the current kernel-DT configuration against the carrier schematic and UPHY allocation, then update the overlay to set the correct lane width.

Install

  1. Download the skill as a ZIP:

    https://mp-staging.autogineer.com/agent-skills/nvidia/jetson-customize-pcie/download

  2. Unzip it into the cross-client skills folder of your project:

    mkdir -p .agents/skills && unzip jetson-customize-pcie.zip -d .agents/skills

Documentation by Jetson Team

Customize PCIe (per-controller status / lanes / speed)

Overview

PCIe on Tegra264 (Thor, [email protected]) and Tegra234 (Orin, [email protected]) is split across multiple controllers that share the UPHY lane pool with USB3 / MGBE / UFS. Each controller's runtime behavior is determined by two surfaces, both required:

SurfaceTargetAuthoritative for
ODMDATA pcie@N_status=… (+ pcie@N_max-link-speed, pcie@N_pcie-mode, pcie@N_clk-scheme, pcie-cN-endpoint-enable)/pcie/pcie@N in BPMP DTBUPHY lane power, refclk gating, controller-side power rails
Kernel-DT overlay on &pcieN/bus@0/pcie@<addr> in kernel DTBKernel probe, lane width, link speed, RC/EP mode

Skipping the kernel overlay on a disable lets the kernel probe a powered-down PHY (link timeouts in dmesg). Skipping the ODMDATA token on a disable leaves BPMP holding the PHY hot.

Agentic, not table-driven — no controller table, no questions.json. Every controller, lane width, schematic-routed receptacle, and authoritative DT node address is discovered at runtime from the docs + DTB + carrier pinmap.

The output is a kernel-DT overlay commit only. Per-controller fragment@N blocks are appended to the composite custom overlay .dts per ../../references/bsp-customization-kernel-dtb.md and committed to the bsp_sources/ hardware repo. /jetson-build-source compiles the composite to .dtbo and owns its Makefile + flash-conf registration.

This skill MUST NOT edit ODMDATA="...". All ODMDATA tokens (pcie@N_status=…, pcie@N_max-link-speed, pcie@N_pcie-mode, pcie@N_clk-scheme, pcie-cN-endpoint-enable, plus the uphyX-config-N surface tokens and UPHY_CONFIG="" clear) are emitted by /jetson-customize-uphy in a single atomic commit on the carrier flash-conf fork. The allocation table this skill consumes from the UPHY sidecar already tells the operator which controllers are okay / disabled / per-lane sized; this skill only translates that table into kernel-DT overlay fragments and verifies that the overlay agrees with the ODMDATA already committed by customize-uphy (consistency check in Step 8 — disagreement is reported, not silently fixed).

When to invoke

  • The user says "configure PCIe", "enable PCIe controller", "set PCIe num-lanes", "change PCIe link speed", or asks to flip a pcie@N_status token.

  • A specific PCIe slot or M.2 receptacle doesn't enumerate after flash, OR the link trains at the wrong width / speed.

  • jetson-customize-uphy ran and re-allocated lanes across PCIe controllers (e.g. switched from uphy0-config-7 to uphy0-config-6 enabling PCIe C3); the per-controller side now needs to be brought up.

  • jetson-customize-mgbe reports the QSFP path is wired but the kernel doesn't probe its PCIe-side companion (rare; XFI configurations).

Prerequisites:

  • Active profile with reference_devkit: + custom_carrier: blocks.

  • <source.root_path>/Linux_for_Tegra/.git exists (/jetson-init-source).

  • /jetson-derive-carrier has run — carrier flash-conf fork is in the overlay tracker.

  • /jetson-customize-uphy has run — its JSON sidecar at <workspace>/target-platform/<profile-stem>.jetson-customize-uphy.json drives the per-controller enable decision.

  • Source-of-truth docs registered or supplied at prompt: Adaptation Guide, Module Design Guide, SoC TRM.

  • When custom_carrier: is present, both documents.custom_carrier_schematic AND documents.custom_carrier_pinmux_xls are REQUIRED. Refuse the run if either is missing — routing on a custom carrier cannot be guessed. Reference-devkit-only profiles skip this check.

  • dtc on PATH.

Procedure (summary)

Full step-by-step walkthrough lives in references/procedure.md. High-level flow:

  1. Resolve active target + open source-of-truth documents (incl. <carrier-pinmap>, <ref-dtb>, <uphy-state>). Refuse if <uphy-state> is missing.

  2. Diff PCIe topology — devkit vs custom carrier — by decompiling <ref-dtb> and grepping the schematic for PEX<N>_* net labels.

  3. AskUserQuestion (multiSelect) — which controllers to customize.

  4. Per-controller verification: pinmap + schematic + pin_verifier.py for PE<N>_CLKREQ_L, PE<N>_RST_L, optional PE<N>_WAKE_L.

  5. Auto-derive per-controller plan (enable from <uphy-state>, lanes / speed from Adaptation Guide, mode hard-pinned to "rc") → mandatory confirm-or-customize gate.

  6. Append per-controller fragment@N blocks (marker /* custom-bsp: pcie:pcie@<addr> */) to the composite custom overlay .dts in bsp_sources/. Pre-flight dtc + fdtoverlay. Commit via the workflow's preview gate. Do not edit ODMDATA — /jetson-customize-uphy already emitted pcie@N_status=…, pcie@N_max-link-speed, pcie@N_pcie-mode, pcie@N_clk-scheme, and pcie-cN-endpoint-enable in its single atomic ODMDATA commit. This skill only translates the per-controller plan into kernel-DT overlay fragments.

  7. (Step folded into Step 6 — overlay-only emission.)

  8. Cross-check ODMDATA vs overlay consistency. On a contradictory row, stop and ask the user how to recover the two commits. Never run git reset --hard autonomously.

  9. Write run-state JSON sidecar at <workspace>/target-platform/<profile-stem>.jetson-customize-pcie.json

    • summary, then drive the downstream next-step chain via sequential AskUserQuestion prompts per references/procedure.md Step 9. Never substitute a printed "Next step: …" line for the prompts.

Limitations

  • Mode hard-pinned to RC. Endpoint mode is only emitted when the operator passes mode_override="ep" in Step 5c.

  • enable is derived, not asked. UPHY-allocated controllers are mandatorily okay; non-allocated are mandatorily disabled.

  • No upstream BSP edits. Output lands in Linux_for_Tegra/ + bsp_sources/ only.

  • Pre-flight overlay merge is a sanity check, not the production build. /jetson-build-source is authoritative.

  • Flash-conf overlay registration is out of scope. Owned by /jetson-build-source Step 5.0a.

Troubleshooting

  • <uphy-state> missing → run /jetson-customize-uphy first.

  • Slot doesn't enumerate after flash → check dmesg | grep pcie; re-verify ODMDATA pcie@<N>_status=okay and the overlay fragment agree (Step 8 table in references/procedure.md).

  • Link trains at wrong width → confirm UPHY config in <uphy-state> allocates the expected lane count; the kernel fragment's num-lanes must match.

  • compatible mismatch → fix the composite root, not the fragment. UEFI plugin-manager silently skips on mismatch.

  • Contradictory ODMDATA-vs-overlay row → ask the user; do not auto-git reset --hard. See gotchas.

  • Common pitfalls — see references/gotchas.md (RC pinning, node- address sourcing, stock-disabled controllers, intra-file handoff with jetson-customize-uphy).

References

  • references/procedure.md — full nine- step procedure (topology diff, plan derivation, overlay append, ODMDATA cross-check, sidecar).

  • references/gotchas.md — failure modes

    • invariants (RC pinning, address sourcing, BPMP handoff).

  • ../../scripts/pin_verifier.py — shared HSIO pin verifier (Step 4).

  • ../../references/platform_template.yaml — documents: block consumed by Step 1.

  • ../../context/bsp-customization-workflow.md — overlay edit protocol + commit message preview gate.

  • ../../references/bsp-customization-kernel-dtb.md — composite overlay filename / skeleton / append protocol.

  • ../jetson-customize-uphy/SKILL.md — sibling skill that owns UPHY lane allocation; its sidecar drives the per-controller enable decision.

  • ../jetson-customize-pinmux/SKILL.md — sibling skill invoked by Step 4 (with operator confirmation) to fix HSIO pin SFIO mismatches.

  • ../jetson-customize-mgbe/SKILL.md — sibling for MGBE controllers; shares the two-surface (ODMDATA

    • overlay) pattern.

  • ../jetson-derive-carrier/SKILL.md — must run first; produces the carrier flash-conf fork edited in Step 6.

  • ../jetson-init-source/SKILL.md — produces the overlay tracker + bsp_sources repo this skill commits into.

Files

BENCHMARK.md

Evaluation Report

Evaluation of the jetson-customize-pcie skill before publication through NVSkills-Eval.

This benchmark summarizes 3-Tier Evaluation from NVSkills-Eval results for the skill. The goal is to document whether the skill is safe, discoverable, effective, and useful for agents before it is published for broader workflow use.

Evaluation Summary

  • Skill: jetson-customize-pcie

  • Evaluation date: 2026-06-16

  • NVSkills-Eval profile: external

  • Environment: astra-sandbox

  • Dataset: 2 evaluation tasks

  • Attempts per task: 1

  • Pass threshold: 50%

  • Overall verdict: PASS

Agents Used

  • claude-code

  • codex

Metrics Used

Reported benchmark dimensions:

  • Security: checks whether skill-assisted execution avoids unsafe behavior such as secret leakage, destructive commands, or unauthorized access.

  • Correctness: checks whether the agent follows the expected workflow and produces the correct final output.

  • Discoverability: checks whether the agent loads the skill when relevant and avoids using it when irrelevant.

  • Effectiveness: checks whether the agent performs measurably better with the skill than without it.

  • Efficiency: checks whether the agent uses fewer tokens and avoids redundant work.

Underlying evaluation signals used in this run:

  • security (Security): checks for unsafe operations, secret leakage, and unauthorized access.

  • skill_execution (Skill Execution): verifies that the agent loaded the expected skill and workflow.

  • skill_efficiency (Efficiency): checks routing quality, decoy avoidance, and redundant tool usage.

  • accuracy (Accuracy): grades final-answer correctness against the reference answer.

  • goal_accuracy (Goal Accuracy): checks whether the overall user task completed successfully.

  • behavior_check (Behavior Check): verifies expected behavior steps, including safety expectations.

  • token_efficiency (Token Efficiency): compares token usage with and without the skill.

Test Tasks

The benchmark dataset contained 2 evaluation tasks:

  • Positive tasks: 2 tasks where the skill was expected to activate.

  • Negative tasks: 0 tasks where no skill was expected.

  • Unlabeled tasks: 0 tasks where positive/negative intent could not be inferred.

Task composition is derived from the evaluation dataset when possible. Entries with expected_skill set are treated as positive skill-activation cases, while entries with expected_skill: null are treated as negative activation cases.

Results

DimensionNumclaude-codecodex
Security2100% (+0%)100% (+0%)
Correctness250% (+30%)85% (+38%)
Discoverability250% (+50%)92% (+42%)
Effectiveness239% (+17%)54% (+32%)
Efficiency259% (+32%)86% (+42%)

Score values show skill-assisted performance. Values in parentheses show uplift versus the no-skill baseline when baseline data is available.

Tier 1: Static Validation Summary

Tier 1 validation passed with observations. NVSkills-Eval ran 1 checks and found 3 total findings.

Top findings:

  • MEDIUM SCHEMA/body_recommended_section: Missing recommended section: '## Instructions' (skills/jetson-customize-pcie/SKILL.md)

  • MEDIUM SCHEMA/body_recommended_section: Missing recommended section: '## Examples' (skills/jetson-customize-pcie/SKILL.md)

  • LOW SCHEMA/author_format: Author must be of the form 'Name <email@host>' (skills/jetson-customize-pcie/SKILL.md)

Tier 2: Deduplication Summary

This tier was not run or did not produce findings in this report.

Publication Recommendation

The skill is suitable to proceed toward NVSkills-Eval publication based on this benchmark. Skill owners should keep this file with the skill and refresh it when the evaluation dataset, skill behavior, or target agents materially change.

Requirements and compatibility

Written for: Claude Code

Works with: Claude Code, Claude apps, OpenAI Codex, GitHub Copilot, Cursor, Gemini CLI, Kiro, OpenCode, Goose, Amp, Roo Code, JetBrains Junie, Factory Droid, Devin (ex-Windsurf), Mistral Vibe, OpenHands, Letta

“Works with” means the tool reads the open Agent Skills format; a skill written for one tool may use features others lack.

Needs: Names Claude Code tools, Needs Node.js

Security

What our scanner noticed· Medium risk

  • Large base64-encoded blobs

A static scan is not a guarantee. Skills are third-party content: review a skill before you let an agent use it.

Attribution and licence

Created by
Jetson Team
Publisher
NVIDIA (Official)
Distributed by
NVIDIA
Source
NVIDIA/skills · skills/jetson-customize-pcie · commit fce3cca
Licence
Apache License 2.0 (redistribution allowed)
  • LICENSE (added by AutoGineer from LICENSE-APACHE)
  • ATTRIBUTION.md (written by AutoGineer)
Synced

AutoGineer is not affiliated with or endorsed by Jetson Team or NVIDIA.

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The ZIP holds the skill’s files, its licence files and an ATTRIBUTION.md. Download jetson-customize-pcie.zip