Jetson Customize Pinmux
NVIDIAOfficialCreated by Jetson TeamDistributed by NVIDIA
- Skill
- Tool integration
- Cloud and DevOps
- Apache-2.0
- Medium risk
- Has scripts
AutoGineer summary
Written by AutoGineer from the skill’s own files, not by the author
The jetson-customize-pinmux skill provides a structured workflow for configuring per-pin SFIO, direction, and initial state for Jetson Orin or Thor custom carriers. It parses the official Tegra pinmux spreadsheet (XLSM) to generate the necessary BCT DTSI files (pinmux, gpio, and padvoltage). The skill ensures that pin configurations are accurately captured, validated, and integrated into the carrier's bootloader configuration, following a strict interactive process to prevent hardware misconfiguration.
What it does
- Parses Tegra pinmux XLSM files to establish a ground truth for SoC pin configurations.
- Provides an interactive lookup tool to identify pins by ball name, signal, or DT name.
- Guides users through a mandatory Q1-Q6 interactive loop to set pin attributes.
- Generates pinmux, gpio, and padvoltage BCT DTSI files for custom carrier boards.
- Updates carrier configuration references to include the newly generated DTSI files.
- Ensures configuration idempotency by using specific markers in the generated files.
When to use it
- When you need to repurpose a CVM ball (e.g., switching between GPIO and a peripheral function).
- After deriving a custom carrier and needing to apply specific pinmux settings from an XLSM.
- When a pin mismatch is reported by other Jetson customization skills.
- When you need to define initial pin states, drive types, or pull attributes for custom hardware.
Advantages
- Ensures consistency by using the official XLSM as the single source of truth.
- Prevents configuration errors through a mandatory, guided per-pin interactive process.
- Automates the complex generation of three distinct BCT DTSI files.
- Integrates cleanly with existing Jetson BSP workflows and overlay trackers.
Usage examples
- “Configure pin H10 on my custom carrier to act as a GPIO.”
- The agent will look up pin H10, confirm it is GPIO-capable, and prompt you through the required direction and initial state settings before generating the updated DTSI files.
- “I need to set the drive type for the PCIE4_RST_L signal.”
- The agent will identify the corresponding DT pin, check if the pad is configurable, and if so, guide you through the Q4-Q6 attributes including drive type.
Install
Download the skill as a ZIP:
https://mp-staging.autogineer.com/agent-skills/nvidia/jetson-customize-pinmux/downloadUnzip it into the cross-client skills folder of your project:
mkdir -p .agents/skills && unzip jetson-customize-pinmux.zip -d .agents/skills
Documentation by Jetson Team
Customize pinmux (per-pin SFIO / direction / state)
Overview
The Tegra pinmux spreadsheet (.xlsm) is the ground truth for every
CVM ball: SoC pin name, supported SFIOs, customer-selected function,
direction, and initial state. This skill parses that XLSM, runs a
per-pin Q1–Q6 interactive loop, and emits the three BCT DTSIs
(pinmux, gpio, padvoltage) in one shot into the overlay tracker
at <source.root_path>/Linux_for_Tegra/bootloader/.
Unlike sibling skills jetson-customize-uphy / jetson-customize-pcie /
jetson-customize-camera, pinmux has no kernel-DT overlay surface and no
ODMDATA edit. The XLSM is the source of truth; the three emitted
DTSIs land at flash time via the carrier conf's
PINMUX_CONFIG= / GPIOINT_CONFIG= / PMC_CONFIG= references (which
/jetson-derive-carrier set up).
Pad classification (silicon-fixed): only BD* and BI* pads have
configurable pull / drive / open-drain attributes. LP5XA_*,
UPHYDS_*, DP_SINGLE_*, BDMIPI16X_*, BDUSB2_*, OSCI27_* are
fixed-function and skip Q4–Q6 (configurable: no).
The bundled scripts/modify_pinmux.py is the workhorse: it parses
the XLSM via openpyxl>=3.1, builds the per-carrier pinmap JSON,
captures pin edits into a session shim, and (on generate) writes
the three DTSIs.
When to invoke
The user says "configure pin", "set SFIO", "edit pinmux DTSI", "set pin direction", "set initial state", or asks to repurpose a CVM ball (e.g. flip a pin between GPIO and a peripheral function).
A sibling skill (
jetson-customize-camera,jetson-customize-pcie,jetson-customize-usb,jetson-customize-mgbe) reports an HSIO pin mismatch viapin_verifier.pyand the user wants to fix it.The user pre-derived a custom carrier with
/jetson-derive-carrierand now wants to author the pinmux from a freshly-edited.xlsm.
Prerequisites:
Active profile selected (
target-platform/active_target.yml→<profile>.yamlwithreference_devkit:ANDcustom_carrier:).<source.root_path>/Linux_for_Tegra/exists as a git repo (/jetson-init-source)./jetson-derive-carrierhas run — the three pinmux-side BCT DTSIs (PINMUX_CONFIG,GPIOINT_CONFIG,PMC_CONFIGreferences in the carrier conf) exist in the overlay tracker.A pinmux
.xlsmis registered in the active profile atdocuments.custom_carrier_pinmux_xls(preferred when custom-carrier- specific) ordocuments.ref_devkit_pinmux_xls(fallback). The bundledmodify_pinmux.pyrequiresopenpyxl>=3.1.
Procedure
See references/procedure.md for the full
step-by-step procedure (Steps 1–8). Summary:
Resolve active target + XLSM. Validate active profile,
custom_carrier:, overlay-tracker prerequisites; resolve the pinmux.xlsmpath fromdocuments.custom_carrier_pinmux_xls→documents.ref_devkit_pinmux_xls→ single XLSM underdocuments.root_path→ user prompt.Probe. Run
modify_pinmux.py probeto parse the XLSM into the per-skill scratch<KB>/pinmap/<custom-carrier>.jsonplussession.jsonshim.Lookup. Resolve a free-form user query (CVM ball, Verilog name, signal, DT pin) via
modify_pinmux.py lookup; surface supported SFIO list, defaults, andconfigurable: yes/no.Set-pin (HARD GATE — Q1–Q6 via
AskUserQuestion). Q1–Q3 (sfio/direction/initial_state) always asked; Q4–Q6 (pull/drive_type/open_drain) only whenconfigurable: yes.tristateande_inputare derived fromdirection, never asked.Generate.
modify_pinmux.py generate --out-dir <source.root_path>/Linux_for_Tegra/bootloader/(root, notbootloader/generic/BCT/— derive-carrier.dtsforks live there, do not colocate). Emits:tegra<soc>-mb1-bct-{pinmux,gpio,padvoltage}-<carrier-key>.dtsi.<carrier-key>comes from the carrier conf'sPINMUX_CONFIG=reference, NOT the kebab-cased carrier name.Commit (single batched commit per workflow rule). All three DTSIs are one logical edit → one customization commit. Run the commit-preview gate before each commit.
Run-state sidecar + session shim. Write the user-facing
<profile-stem>.jetson-customize-pinmux.jsonsidecar and the transientsession.jsonshim under<workspace>/target-platform/.Summary. Emit the standard one-line + table summary.
Gotchas
No kernel-DT overlay; no
OVERLAY_DTB_FILEedit; norender_conf.pyhand-off. This skill ends at the three BCT DTSIs — the carrier conf already references them viaPINMUX_CONFIG=/GPIOINT_CONFIG=/PMC_CONFIG=(set up by/jetson-derive-carrier).Re-point the
.dtswrapper's#includeaftergenerate./jetson-derive-carrierforks the.dtswrappers atbootloader/generic/BCT/, but their#includelines may still pull the upstream devkit.dtsi(e.g.…-p3834-xxxx-p4071-0000.dtsi). Aftergeneratewrites the new<CARRIER_KEY>.dtsitobootloader/root, edit each wrapper's#includeto the new filename — by bare basename (#include "tegra<soc>-mb1-bct-pinmux-<CARRIER_KEY>.dtsi"), not../../…filesystem-relative. The BCT build'scpp -I bootloader/resolves bare basenames; that's the convention every other BCT include in the tree follows. Roll the wrapper edits into the same customization commit as the three DTSIs. Seereferences/procedure.mdStep 5 ("Sanity-check the carrier.dtswrapper").Q4–Q6 gated on
configurable: yes. Asking pull / drive_type / open_drain on a fixed-function pad (LP5XA_*,UPHYDS_*,BDMIPI16X_*, etc.) is silently dropped by the script and confuses the user.lookupprintsconfigurable: yes/no— always check it before prompting Q4–Q6.tristateande_inputare derived, never asked.unused→ tristate=ENABLE;input/bidirectional→ enable-input=ENABLE. Exposing them as separate prompts produces inconsistent DTSIs.sfio=gpiorequires a parseablegpio=GPIOn_PD.NNentry in the pinmap row'ssfiolist. Pins without one are GPIO-incapable silicon;set-pinrejects the call. Surface the rejection — don't silently fall back to a non-GPIO SFIO.Marker idempotency. Every per-pin edit carries
// custom-bsp: pinmuxon the closing brace; gpio default-state entries carry the same marker as a trailing comment. Re-runninggeneratemust detect and update — never duplicate.modify_pinmux.pyis unchanged from the original framework — it reads its ownsession.jsonshim under--kb-dir. The shim is regenerated each run from the active profile + the user-facing sidecar. Do not hand-edit the shim; it's transient.Multiple pinmux DTSI variants per Thor module SKU. Some carrier pins live in a different DTSI variant than the one the carrier conf references.
modify_pinmux.py commit(legacy patch-in-place flow) tolerates missing per-pin blocks viapinmux.warnings[]rather than failing. Surface the warning; point at the alternate DTSI variant.Don't touch the upstream BSP at
<bsp_image.root_path>. All edits land in<source.root_path>/Linux_for_Tegra/bootloader/under the pristine + customization commit pattern.
Available Scripts
| Script | Purpose | Arguments |
|---|---|---|
scripts/modify_pinmux.py | XLSM parser + per-pin DTSI generator. Invoked via run_script() from Steps 3-6 with the subcommand of the current phase. | probe | lookup | set-pin | apply | generate | commit [...] (see --help) |
scripts/generate_dtsi.py | Renders pinmux/GPIO/padvoltage DTSI fragments from the bundled session state. Called by modify_pinmux.py generate. | --session <path> --out-dir <dir> |
Invoke from the skill body as a subprocess via run_script():
# run_script: probe the carrier pinmux XLSM and write a session state
scripts/modify_pinmux.py probe --xlsm carrier.xlsm --session .pinmux-session.json
# run_script: render DTSI fragments from the final session state
scripts/modify_pinmux.py generate --session .pinmux-session.json --out-dir bsp_sources/pinmux/References
references/procedure.md— full Step 1–8 procedure prose.questions.json— Q1–Q6 prompt schema consumed by Step 4.../../references/platform_template.yaml—documents:block (ref_devkit_pinmux_xls,custom_carrier_pinmux_xls).../../context/bsp-customization-workflow.md— overlay edit protocol (single-commit per DTSI fork).../jetson-derive-carrier/SKILL.md— must run first; produces the pinmux / gpio / padvoltage DTSI forks this skill edits, and rewrites the carrier conf'sPINMUX_CONFIG=/GPIOINT_CONFIG=/PMC_CONFIG=lines to point at them.../jetson-init-source/SKILL.md— produces the overlay tracker this skill commits into.../jetson-link-docs/SKILL.md— author the profile'sdocuments:block, including the pinmux XLSM bindings.
Files
- ATTRIBUTION.mdAdded by AutoGineer932 B
- BENCHMARK.md3.9 KiB
- LICENSELicence file added by AutoGineer11.2 KiB
- SKILL.md9.5 KiB
- evals/evals.json4.0 KiB
- questions.json2.5 KiB
- references/procedure.md16.6 KiB
- scripts/_pinmux_common.pyScript8.2 KiB
- scripts/_pinmux_dt.pyScript8.9 KiB
- scripts/generate_dtsi.pyScript32.8 KiB
- scripts/modify_pinmux.pyScript29.4 KiB
- skill-card.md3.5 KiB
- skill.oms.sig5.9 KiB
references/procedure.md
jetson-customize-pinmux — Detailed Procedure
Detailed step-by-step procedure for the jetson-customize-pinmux skill.
The SKILL.md keeps a short summary; this file holds the full prose.
Step 1 — Resolve active target + XLSM
Resolve the active profile per target-platform-contract.md
(in ../../context/).
Refuse conditions:
| Condition | Reason |
|---|---|
No active profile (active: NA) | Run /jetson-init-target first. |
custom_carrier: missing | Pinmux customization is carrier-specific. |
<source.root_path>/Linux_for_Tegra/.git missing | Run /jetson-init-source first. |
| Carrier conf fork missing from overlay tracker | Run /jetson-derive-carrier first. |
No documents.{custom_carrier_pinmux_xls,ref_devkit_pinmux_xls} AND no .xlsm found under documents.root_path | Prompt for an absolute path; abort if user doesn't provide one. |
Identifiers from the profile:
| Var | Source |
|---|---|
<chip> | reference_devkit.module.id → catalogue (T234 / T264) |
<soc> | 264 (Thor) / 234 (Orin) |
<custom-carrier> | kebab-cased custom_carrier.name |
<custom-flash-conf> | custom_carrier.flash_config |
Resolve <xlsm> path (precedence order):
documents.custom_carrier_pinmux_xlsif set.documents.ref_devkit_pinmux_xlsif set.Single
.xlsmunder<documents.root_path>/(one-level scan).Prompt for absolute path; record in run-state but do not write back to the profile.
Step 2 — Probe — parse the XLSM, build the pinmap
The bundled script writes its own KB into a per-skill scratch
directory under target-platform/:
<workspace>/target-platform/<profile-stem>.jetson-customize-pinmux/
├── session.json # shim for modify_pinmux.py --kb-dir
└── pinmap/
└── <custom-carrier>.jsonGenerate the session shim first (one-time per run, before any script call) — see Step 7 for the schema. Then run:
KB=<workspace>/target-platform/<profile-stem>.jetson-customize-pinmux
python3 <skill-base>/scripts/modify_pinmux.py probe \
--xlsm <resolved xlsm path> \
--carrier-name <custom-carrier> \
--kb-dir "$KB"probe writes <KB>/pinmap/<custom-carrier>.json and updates
<KB>/session.json with xlsm_path + carrier_name. No DTSIs are
written yet.
If exactly one .xlsm matched the search in Step 1, ask the user to
confirm (don't auto-bind).
Step 3 — Lookup — resolve a user query to one or more pinmap rows
The user does NOT need to know the DT pin name. They type whatever they have on hand:
CVM ball (
H10)Verilog name (
PEX_L4_RST_N)Carrier signal name (
PCIE4_RST_L,CAM0_I2C_SCL,GPIO47)DT pin name (
pex_l4_rst_n_pd1)
python3 <skill-base>/scripts/modify_pinmux.py lookup \
--kb-dir "$KB" --query "<X>"Case-insensitive match across dt_pin_name / pin, cvm_pin /
ball, verilog_name, signal_name, and any token in
evidence[].net. The output prints supported SFIO list (with
(suggested) on the SFIO matching customer_usage), default
direction, default initial-state, customer-usage note, and a
configurable: yes/no line.
Match-count handling:
0 matches — script prints up to 5 closest substring candidates ("did you mean…?") and exits non-zero. Surface to user.
1 match — proceed to Step 4.
>1 matches — list all candidates and require the user to disambiguate by DT pin name on the next call. Never silently pick.
Step 4 — Set-pin — capture the per-pin Q1–Q6 flow
HARD GATE — ask the user, do not infer. Per-pin SFIO / direction /
state / pull / drive / open-drain are the load-bearing choices of this
skill. The model MUST drive Q1–Q6 through AskUserQuestion (one
prompt per pin, options sourced from sfio_options + the XLSM
defaults shown by lookup). No-stop / quiet-mode / "resume"
instructions DO NOT bypass this gate — they cover prereqs and
defaults, not the primary user decision. If the user declines to
answer, stop the run with no edits committed; never substitute a
silent default like "keep as customer_usage suggests".
Run the question flow from questions.json for each pin the user
picked in Step 3 (any of the input forms listed in Step 3 are valid;
lookup resolves them uniformly). Q1–Q3 are always asked; Q4–Q6 are
gated on configurable: yes.
Q1–Q3 (always asked):
sfio— single-select from the supported list.(suggested)tags the XLSMcustomer_usagematch. Validate membership. If the list has only one entry, still show it and ask — never silently auto-select.direction—input/output/bidirectional/unused.tristateande_inputin the DTSI are derived from direction (unused→ tristate=ENABLE;input/bidirectional→ enable-input=ENABLE) — never asked separately.initial_state—low/high/hi-z/n/a. For non-output pins the only valid value isn/a. Maps to XLSMgpio_init_val(0→low,1→high,z→hi-z).
Q4–Q6 (only when configurable: yes):
pull—none/pull-up/pull-down. Pre-fill fromdefault_pull(XLSMpupd). Resistor is silicon-fixed at 20 kΩ.drive_type—normal(1X) /high(2X). Pre-fill fromdefault_drv_type(drv_type). Hint: QSPI SCK / IO SFIOs (qspi*_sck/qspi*_io) default tohigh(2X); SDMEM pads showingDEF_1Xraw →normal.open_drain—disable/enable. Pre-fill fromdefault_open_drain(e_io_od). Hint: XLSM setse_io_od=Enablefor I2C (i2c*_clk/i2c*_dat), HDMI CEC (hdmi_cec), PCIe CLKREQ / RST (pe*_clkreq_l/pe*_rst_l), SHUTDOWN_N, and DPAUX-routed I2C (dp_aux_*). When the chosen SFIO matches one of these and pre-fill isenable, surface as required.
loopback (e_lpbk) is not asked unless the user explicitly
requests it (only QSPI0 / QSPI2 SCK have e_lpbk=Enable on Thor).
Informational only (shown by lookup, not settable): por_state
(pu/pd/z/0/1), pull_strength (20 kΩ on BD* pads;
N/A on DPAUX).
After Q1–Q3 (or Q1–Q6) for each pin, call:
python3 <skill-base>/scripts/modify_pinmux.py set-pin \
--kb-dir "$KB" \
--pin <dt_pin_name> \
--sfio <sfio> \
--direction <direction> \
--initial-state <initial_state> \
[--pull <pull>] [--drive-type <drv>] [--open-drain <od>]The call validates the SFIO is in the supported list (rejects
otherwise) and appends / merges-by-pin into the run-state's
pin_edits[]. Repeat Steps 3 + 4 for every pin to modify.
Step 5 — Generate — emit the three DTSIs in one shot
After all pin edits are collected, run:
OUT=<source.root_path>/Linux_for_Tegra/bootloader
python3 <skill-base>/scripts/modify_pinmux.py generate \
--kb-dir "$KB" \
--out-dir "$OUT"This applies the captured pin_edits to the XLSM data and writes:
tegra<soc>-mb1-bct-pinmux-<carrier-key>.dtsi— per-pin blocks settingnvidia,function = "<sfio>",nvidia,enable-input,nvidia,tristate. Closing brace carries// custom-bsp: pinmuxmarker (idempotency).tegra<soc>-mb1-bct-gpio-<carrier-key>.dtsi— persfio=gpiopin, appends / updates entries under the matchinggpio@<addr>controller'sdefault { ... }:input→gpio-input;output + low→gpio-output-low;output + high→gpio-output-high. Controller node (gpio@ac300000for Thor MAIN, etc.) is selected from theGPIOn_*bank prefix in the pinmap row'ssfiolist. Pins lacking agpio=…entry in their SFIO list are rejected atset-pintime.tegra<soc>-mb1-bct-padvoltage-<carrier-key>.dtsi— no per-pin edits in the current flow; rewritten from XLSM data.
<carrier-key> matches the rename pattern /jetson-derive-carrier
chose (<module-id-num>-xxxx-<custom-id>-<custom-sku> or similar) —
the exact filenames referenced from the carrier conf's
PINMUX_CONFIG= / GPIOINT_CONFIG= / PMC_CONFIG= lines. Generate
writes to those exact paths so the carrier conf needs no edits here.
Resolve <carrier-key> at runtime — DO NOT pass the bare carrier
name. The script's --carrier-name is used verbatim as the filename
suffix; passing the kebab-cased custom-carrier name (e.g. ken)
produces tegra<soc>-mb1-bct-pinmux-ken.dtsi, which the carrier conf
does NOT reference and which are orphan files at flash time.
Instead, derive <carrier-key> from the active flash-conf fork:
CONF=<source.root_path>/Linux_for_Tegra/$(readlink \
<source.root_path>/Linux_for_Tegra/<custom_carrier.flash_config>)
PINMUX_REF=$(grep '^PINMUX_CONFIG=' "$CONF" | cut -d'"' -f2)
# e.g. "tegra264-mb1-bct-pinmux-p3834-xxxx-p6767-0002.dts"
CARRIER_KEY=$(echo "$PINMUX_REF" \
| sed -E "s|^tegra[0-9]+-mb1-bct-pinmux-(.*)\.dtsi?$|\1|")
# CARRIER_KEY = "p3834-xxxx-p6767-0002"Pass --carrier-name "$CARRIER_KEY" to every probe / generate
call. With the key derived this way, generate overwrites the
derive-carrier .dtsi forks in place, and the carrier conf's
PINMUX_CONFIG= / PMC_CONFIG= references resolve correctly with
no conf edit. The kebab-cased custom-carrier name remains the right
input for SCRATCH PATHS only (the per-skill scratch directory under
target-platform/, and the pinmap JSON filename
<custom-carrier>.json).
Sanity-check the carrier .dts wrapper's #include line (REQUIRED).
/jetson-derive-carrier forks the .dts wrapper at
bootloader/generic/BCT/tegra<soc>-mb1-bct-{pinmux,padvoltage}-<CARRIER_KEY>.dts
but its #include "..." may still point at the upstream devkit .dtsi
(e.g. tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000.dtsi). After
generate writes the new carrier-key .dtsi to bootloader/ root, the
wrapper must include the new file — otherwise the carrier conf still
sources the upstream devkit pinmux at flash time and your edits are
silently ignored. For each wrapper that needs it:
/* before */
#include "tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000.dtsi"
/* after */
#include "tegra264-mb1-bct-pinmux-<CARRIER_KEY>.dtsi" /* custom-bsp: pinmux */Use a bare basename, not a filesystem-relative path. The BCT build
runs cpp -I bootloader/ so the resolver picks up sibling .dtsi
files regardless of where the .dts wrapper lives in
bootloader/generic/BCT/. Authoring ../../tegra264-mb1-bct-…dtsi
works but breaks the convention used by every other BCT include in the
tree. Stage the wrapper edit and roll it into the same commit as the
three DTSIs in Step 6.
Step 6 — Commit the three DTSIs in the overlay tracker
The three DTSIs generate produced under
<source.root_path>/Linux_for_Tegra/bootloader/ are a single
logical edit, so they get committed as one batched pair per the
overlay-tracker commit-batching rule in
bsp-customization-workflow.md (#commit-batching-in-the-overlay-tracker,
under ../../context/):
Pristine import (one commit, skip if unnecessary). If any of the three DTSIs lack a prior pristine import commit (rare —
/jetson-derive-carriershould have created them), import the pre-edit copies via XLSM regeneration and commit all newly imported files in a single pristine commit. If all three already have pristine imports from/jetson-derive-carrier, skip this.Customization (one commit, always).
git addall three DTSIs and any carrier.dtswrapper whose#includewas re-pointed in Step 5's sanity-check, then commit once with a singlejetson-customize-pinmux:message that names every pin changed plus a one-line summary per DTSI.
Never produce three separate per-DTSI customization commits — the batched single commit is what the workflow's commit-batching rule mandates for multi-file logical edits in the overlay tracker.
Preview gate (required, per commit). Before running git commit
for either the pristine import or the customization, render git diff --staged --name-status plus the proposed commit message to
the operator and obtain accept / edit / cancel per the workflow
"Commit message preview gate" section (in bsp-customization-workflow.md).
On cancel, leave the index staged and exit without committing —
do not auto-commit.
Step 7 — Run-state JSON sidecar + session shim
Two artifacts:
User-facing sidecar at
<workspace>/target-platform/<profile-stem>.jetson-customize-pinmux.json:
{
"generator": "jetson-customize-pinmux",
"generator_version": "0.1.0",
"generated_at": "<ISO-8601 UTC timestamp>",
"active_profile": "<profile-stem>.yaml",
"bsp_version": "<bsp_image.version>",
"xlsm_path": "<resolved absolute path>",
"carrier_name": "<custom-carrier>",
"pin_edits": [
{
"pin": "pex_l4_rst_n_pd1",
"ball": "H10",
"verilog_name": "PEX_L4_RST_N",
"signal_name": "PCIE4_RST_L",
"sfio": "gpio",
"direction": "output",
"initial_state": "high",
"pull": "pull-up",
"drive_type": "normal",
"open_drain": "disable",
"configurable": true,
"evidence": "user",
"reason": "M.2 NVMe slot CLKREQ reset"
}
],
"dtsis_written": [
"<source.root_path>/Linux_for_Tegra/bootloader/tegra<soc>-mb1-bct-pinmux-<carrier-key>.dtsi",
"<source.root_path>/Linux_for_Tegra/bootloader/tegra<soc>-mb1-bct-gpio-<carrier-key>.dtsi",
"<source.root_path>/Linux_for_Tegra/bootloader/tegra<soc>-mb1-bct-padvoltage-<carrier-key>.dtsi"
],
"warnings": [],
"notes": [],
"commit_shas": {
"overlay_tracker": "<short SHA>"
}
}Script-internal session.json shim at
<workspace>/target-platform/<profile-stem>.jetson-customize-pinmux/session.json:
{
"platform": "thor" | "orin",
"carrier_short": "<custom-carrier>",
"carrier_name": "<custom-carrier>",
"reference_conf": "<reference_devkit.flash_config>",
"xlsm_path": "<resolved absolute path>",
"cloned_pinmux_dtsi": "<source.root_path>/Linux_for_Tegra/bootloader/tegra<soc>-mb1-bct-pinmux-<carrier-key>.dtsi",
"cloned_gpio_dtsi": "<source.root_path>/Linux_for_Tegra/bootloader/tegra<soc>-mb1-bct-gpio-<carrier-key>.dtsi",
"pinmux": {
"pin_edits": [],
"notes": [],
"warnings": []
}
}Atomic write for both: write .tmp sibling then rename. The
session.json shim is the script's working state and is regenerated
each run from the user-facing sidecar + active profile.
Idempotency contract: re-runs read the user-facing sidecar to
surface prior pin_edits as a starting list; the user can add,
modify, or remove entries. If no edits change between runs, Steps 5
6 emit
(no change)and skip the rewrite.
Step 8 — Summary
Print one block:
jetson-customize-pinmux: <N> pin edit(s) emitted to <carrier-key> DTSIs; commit <short SHA>.| Field | Value |
|---|---|
| Active profile | target-platform/<profile-stem>.yaml |
| Custom carrier | <custom_carrier.name> (<custom-id>-<custom-sku>) |
| Pinmux XLSM | <xlsm path> |
| Pin edits | one row per pin_edits[] entry: pin / ball / SFIO / direction / initial / (pull, drv, od when configurable) |
| DTSIs written | three paths under <source.root_path>/Linux_for_Tegra/bootloader/ |
| Commit SHA | <source.root_path>/Linux_for_Tegra → <short SHA> (single commit covering all three DTSIs) |
| Run-state sidecar | <workspace>/target-platform/<profile-stem>.jetson-customize-pinmux.json |
| Session shim | <workspace>/target-platform/<profile-stem>.jetson-customize-pinmux/session.json |
| Warnings | newline-separated warnings[] (e.g. pins skipped by commit, missing per-pin blocks) |
| Notes | newline-separated notes[] |
Next step (interactive prompt chain):
After the summary table is printed, drive the downstream chain via
sequential AskUserQuestion prompts. Never auto-invoke; each prompt
needs an explicit yes. On no (or any abort), print the remaining
manual run-chain and exit.
In order:
Customize any other I/O before build? — offer
/jetson-customize-uphy,/jetson-customize-pcie,/jetson-customize-mgbe,/jetson-customize-usb,/jetson-customize-camera,/jetson-customize-clocks,/jetson-customize-fan,/jetson-customize-nvpmodel,/jetson-customize-memory, andno(proceed). On any non-nopick, invoke the chosen sub-skill inline; when it returns, re-ask this same question (loop) until the user picksno. Then continue to (2).Build & promote? — on
yesinvoke/jetson-build-source(skip if no source-tree repo was touched this session — pinmux-only edits land in the overlay tracker), then on success invoke/jetson-promote-image.Flash the board? — only offer if (2) ran and succeeded; on
yesinvoke/jetson-flash-image.Validate on the DUT? — only offer if (3) ran and succeeded; on
yesinvoke/jetson-validate-image.
Requirements and compatibility
Written for: Claude Code
Works with: Claude Code, Claude apps, OpenAI Codex, GitHub Copilot, Cursor, Gemini CLI, Kiro, OpenCode, Goose, Amp, Roo Code, JetBrains Junie, Factory Droid, Devin (ex-Windsurf), Mistral Vibe, OpenHands, Letta
“Works with” means the tool reads the open Agent Skills format; a skill written for one tool may use features others lack.
Needs: Names Claude Code tools, Needs Python
Security
What our scanner noticed· Medium risk
- Large base64-encoded blobs
- Scripts that your agent may run
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Attribution and licence
- Created by
- Jetson Team
- Publisher
- NVIDIA (Official)
- Distributed by
- NVIDIA
- Source
- NVIDIA/skills · skills/jetson-customize-pinmux · commit fce3cca
- Licence
- Apache License 2.0 (redistribution allowed)
- LICENSE (added by AutoGineer from LICENSE-APACHE)
- ATTRIBUTION.md (written by AutoGineer)
- Synced
AutoGineer is not affiliated with or endorsed by Jetson Team or NVIDIA.
Download ZIP
The ZIP holds the skill’s files, its licence files and an ATTRIBUTION.md. Download jetson-customize-pinmux.zip